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SRFLIPFLOP
SR flip-flop
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Description
This block describe the simplest and the most fundamental latch the SR flip flop. Where S and R are the input and Q and !Q are the outputs.If S (Set) is pulsed high while R is held low, then the Q output is forced high, and stays high when S returns low; similarly, if R (Reset) is pulsed high while S is held low, then the Q output is forced low, and stays low when R returns low. When both are low, Q(t) takes the same state as Q(t-1). When they are both high, both Q and !Q take the low values we are in an unstable state. Practically we have to avoid this case.This block is almost used with digital number, the input data type is int8.
The truth table of this block is
| S | R | Q(t) | !Q(t) |
| 0 | 0 | Q(t-1) | !Q(t-1) |
| 0 | 1 | 0 | 1 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 0 |
| -> This case is to avoid |
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Initial Value
Initial Value of the state Q.
Properties : Type 'vec' of size 1.
Default properties
always active: no
direct-feedthrough: yes
zero-crossing: no
mode: no
regular inputs:
- port 1 : size [1,1] / type 5
- port 2 : size [1,1] / type 5
regular outputs:
- port 1 : size [1,1] / type 5
- port 2 : size [1,1] / type 5
number/sizes of activation inputs: 0
number/sizes of activation outputs: 0
continuous-time state: no
discrete-time state: no
object discrete-time state: no
name of computational function: csuper
Interfacing function
SCI/modules/scicos_blocks/macros/IntegerOp/SRFLIPFLOP.sci
Compiled Super Block content
Authors
Fady NASSIF - INRIA
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