Scilab Website | Contribute with GitLab | Mailing list archives | ATOMS toolboxes
Scilab Online Help
2023.0.0 - 日本語


VVsourceAC

Variable AC voltage source

Block Screenshot

Description

The variable voltage source block is a model for a controlled AC voltage source. This component provides a sinusoid voltage across its ports. The amplitude of the output voltage is governed by the explicit input and the frequency is defined by the user. The ohmic resistance of the block is zero.

Parameters

  • Frequency (Hz)

    Frequency of the output sinusoid voltage

    Properties : Type 'vec' of size -1.

Default properties

  • Inputs :

    • Modelica variable name : 'p'

      Implicit variable.

    • Modelica variable name : 'VA'

      Explicit variable.

  • Outputs :

    • Modelica variable name : 'n'

      Implicit variable.

  • Parameters :

    • Modelica parameter name : 'f'

      Default value : 50

      Is a state variable : no.

  • File name of the model : VVsourceAC

Interfacing function

  • SCI/modules/scicos_blocks/macros/Electrical/VVsourceAC.sci

Modelica model

  • SCI/modules/scicos_blocks/macros/Electrical/VVsourceAC.mo

Report an issue
<< Switch Electrical palette VariableResistor >>

Copyright (c) 2022-2023 (Dassault Systèmes)
Copyright (c) 2017-2022 (ESI Group)
Copyright (c) 2011-2017 (Scilab Enterprises)
Copyright (c) 1989-2012 (INRIA)
Copyright (c) 1989-2007 (ENPC)
with contributors
Last updated:
Tue Mar 07 09:28:57 CET 2023