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Manual Scilab >> xcos > palettes > Integer palette > LOGIC

LOGIC

Combinational Logic

Block Screenshot

Description

This block implements a standard truth table for modeling programming array, digital circuit and any other boolean expressions. The user can specify a matrix that defines all the possible block output in the Truth table field. Each row of the matrix contains the output of different combination of input elements. The number of rows must be a power of two, it defines the number of inputs using the equation:

number of row = 2 (number of input)

The number of outputs is equal to the number of columns of the matrix.

This block support only the int8 data type. When the input is positive, the input is considered as logical 1, When it is negative or zero it is considered as logical 0.

This block can be activated by an implicit input event or it can inherit the clock from the regular input.

This block is used to implement SR and JK flip-flops.

Dialog box

  • Truth table

    The matrix of outputs. For more information see the description part.

    Properties : Type 'mat' of size [-1,-2].

  • Inherit(0=no 1=yes)

    Specifies if the clock is inherit or not.

    Properties : Type 'vec' of size 1.

Example

The easiest example to consider is the OR example. In this case we have two inputs and only one output.the truth table for this example is [0;1;1;1].
|-----------|-----------|-----------| 
|  input 1  |  input 2  |  output   | 
|-----------|-----------|-----------| 
|     0     |     0     |     0     | 
|-----------|-----------|-----------| 
|     0     |     1     |     1     | 
|-----------|-----------|-----------| 
|     1     |     0     |     1     | 
|-----------|-----------|-----------| 
|     1     |     1     |     1     | 
|-----------|-----------|-----------|

Default properties

  • always active: no

  • direct-feedthrough: yes

  • zero-crossing: no

  • mode: no

  • regular inputs:

    - port 1 : size [1,1] / type 5

    - port 2 : size [1,1] / type 5

  • regular outputs:

    - port 1 : size [1,1] / type 5

  • number/sizes of activation inputs: 1

  • number/sizes of activation outputs: 0

  • continuous-time state: no

  • discrete-time state: no

  • object discrete-time state: no

  • name of computational function: logic

Interfacing function

  • SCI/modules/scicos_blocks/macros/IntegerOp/LOGIC.sci

Computational function

  • SCI/modules/scicos_blocks/src/c/logic.c

Authors

Fady NASSIF - INRIA

Scilab Enterprises
Copyright (c) 2011-2017 (Scilab Enterprises)
Copyright (c) 1989-2012 (INRIA)
Copyright (c) 1989-2007 (ENPC)
with contributors
Last updated:
Wed Jan 26 16:24:42 CET 2011